1. Field of the Invention
The present invention relates to a timing adjustment circuit and a semiconductor device. More particularly, the present invention relates to a timing adjustment circuit for adjusting timing between a data signal and a clock signal that determines the timing of latching the data signal. The present invention also relates to a semiconductor device having such a timing adjustment circuit.
2. Description of the Related Art
Semiconductor memory products, such as a DDR (double-data-rate) DRAM device, use a data strobe signal DQS (or DQSB) input to a DQS terminal as an input clock signal for fetching or latching a data signal DQ input through a DQ terminal. Such semiconductor memory products are accompanied by a problem that the input setup time (tS) and the hold time (tH) for the latching are degraded due to varied delays of rising edges and falling edges of the internal clock generated from the DQS signal as well as due to the delay of the transmitting-side device. Techniques for avoiding this problem and improving the operational tolerance for the setup time and the hold time defined for an input data signal include the technique described in Patent Publication JP-2001-126481A.
FIG. 8 of the accompanying drawings is a schematic circuit diagram of a semiconductor integrated circuit described in JP-2001-126481A. Referring to FIG. 8, a data strobe signal input from a DQS terminal 201 is then input to a latch-signal generation circuit 235 by way of an input circuit 204, and the latch-signal generation circuit 235 generates a latch signal SA for a 0°-edge (rising edge) and a latch signal SB for a 180°-edge (falling edge). A data signal input from a DQ terminal 202 is then input to a delay circuit 228 by way of an input circuit 219, and the delay circuit 228 delays the data signal by a predetermined time period before it outputs a to-be-latched signal SC. The to-be-latched signal SC is then latched by a S-flip-flop 232 for a 0°-edge by means of latch signal SA and then by a S-flip-flop 233 for a 180°-edge by means of latch signal SB.
A latch-signal generation-control circuit 236 controls latch-signal generation circuit 235. The latch-signal generation-control circuit 236 has an oscillation circuit 269, and the signal SD and the inverted signal /SD generated by the oscillation circuit 269 are input to dummy-latch-signal generation circuits 271, 273 by way of dummy input circuits 270, 272 respectively. A comparator circuit 274 receives, as inputs thereof, the dummy latch signal DSA generated by the dummy-latch-signal generation circuit 271 and corresponds to the latch signal SA, and the dummy latch signal DSB generated by the dummy-latch-signal generation circuit 273 and corresponds to the latch signal SB. The comparator circuit 274 outputs control signals H1 through H3 and L1 through L3 to the dummy-latch-signal generation circuits 271, 273, respectively, based on the result of the comparison so as to allow their rising timings to match with each other. The control signals H1 through H3 and L1 through L3 are also input to the latch-signal generation circuit 235, whereby the rising edge of the latch signal SA and the rising edge of the latch signal SB are equalized.
Techniques for adjusting timing between a data strobe signal and a data signal include the technique described in Patent Publication JP-2003-99321A. With this technique, a known data is written at a specific address of a memory from a memory controller at the time of initializing the memory system and then read out, while changing the delay time of the data strobe signal. Thereafter, the read out data and the written data are compared against each other to determine the range of delay time where a data can be read out correctly. Then, an intermediate value in the range of delay time as determined in the manner as described above is defined as a delay time of the data strobe signal upon reading the data by the memory controller. According to the JP-2003-99321A, it is possible to optimally define the delay time of a data strobe signal with this arrangement so that a read-in data can be accurately latched within a readable time range.
Patent Publication PCT-WO99/46687 describes a technique of comparing a reference signal and a data signal for the phase difference at the data receiving side for the transmission of parallel data, and the data transmitting side adjusts the delay time based on the phase difference. FIG. 9 of the accompanying drawings is a schematic circuit diagram of the data transmission apparatus described in PCT-WO99/46687. Referring to FIG. 9, a simultaneous-arrival 20 judging circuit 326 of a receiver RCV detects the range of variation of data arrivals from a 4-bit data and transmits the result of detection to a delay-time adjustment circuit 306 of a driver DRV. The delay-time adjustment circuit 306 adjusts the delay times of the delay circuits 301 through 304 by individually advancing or delaying, whichever appropriate, the starting time of a signal showing a late or early arrival time, thereby allowing the signals DQ0 through DQ3 to reach the receiver RCV at the same time.
According to the technique of JP-2001-126481A, the difference of delay between the rising edge and the falling edge is compensated; however, the adjustment of the delay time relative to the delay circuit 228 is not conducted. The technique of PCT-WO99/46687 involves a problem that a data has to be read out repeatedly from the memory when determining the range of delay time for correctly reading the data signal, thereby causing that the adjustment operation is time consuming. Additionally, if this technique is applied to an operation of adjusting a strobe signal when latching a data to be written at the memory side, a known data needs to be used as the data signal to be written for the purpose of judging whether or not the data can be written correctly. Therefore, the delay time of the strobe signal cannot be dynamically adjusted by this technique while allowing the memory to be actually operated.
The technique described in PCT-WO99/46687 is used for adjusting the phase difference between parallel data, and thus not for adjusting the phase difference between the data strobe signal and the data signal. Furthermore, with the technique of PCT-WO99/46687, a receiver for detecting the phase difference between data signals and a driver for adjusting the delay time so as to eliminate the detected phase difference have to be combined together for operation. In other words, the phases of parallel data cannot be adjusted by the receiver alone. Therefore, when a known driver (memory control circuit) is used, it is not possible for the receiver (memory device) to adjust the phases of parallel data. This fact means the disadvantage of the described technique in lacking a broad applicability.
In view of the above-described problems of the conventional techniques, it is an object of the present invention to provide a timing adjustment circuit that can dynamically adjust the phase difference between the data signal and the timing signal for latching the data signal only at the data receiving-side device.
It is another object of the present invention to provide a semiconductor device having such a timing adjustment circuit.
The present invention provides a timing adjustment circuit for controlling timing for latching a data signal based on an external timing signal, the timing adjustment circuit including: a variable delay circuit for delaying the external timing signal by a variable delay time to generate a delayed timing signal; a first latch circuit for latching the data signal based on a first clock signal having a specific phase relationship with respect to the delayed timing signal; a second latch circuit for latching the data signal based on a second clock signal having a first delay time with respect to the first clock signal; a third latch circuit for latching the data signal based on a third clock signal having a second delay time with respect to the first clock signal, the second delay time being larger than the first delay time; and a judging circuit for comparing output data of the first through third latch circuits among each other, to control the variable delay time based on a result of comparison.
In the timing adjustment circuit of the present invention, three latch circuits latch the data signal at the respective timings which have a specific phase relationship with respect to the delayed timing signal, the data of the data signal thus latched are compared against one another, and result of the comparison is used for changing the delay time for the delayed timing signal. If the setup time and hold time are suitably set for the data signal with respect to the external timing signal, the data of the outputs of the three latch circuits coincide with one another without adjusting the variable delay time; and if not, the variable delay time is adjusted until the three data coincide with one another for assuring the suitable setup time and hold time.
The specific phase relationship between the delayed timing signal and the first through third clock signals may be selected as desired. For example, the delayed timing signal may be used as the first clock signal.
The present invention also provides a semiconductor device including the timing adjustment circuit of the present invention, and an internal circuit for receiving the output data of the second latch circuit. The semiconductor device may be a DRAM device.
The present invention also provides a semiconductor device including a data terminal, a first timing adjustment circuit configured by the timing adjustment circuit of the present invention, and a second timing adjustment circuit configured by the timing adjustment circuit of the present invention, wherein the first timing adjustment circuit latches a first data signal based on a rising edge of the external timing signal and the second timing adjustment circuit latches a second data signal based on a falling edge of the external timing signal. The semiconductor device may be a DDR DRAM device.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.